Edge Silicon Lab (edgesiliconlab.com) is an independent hardware engineering and systems architecture publication focused on neural processing units (NPUs), on-device artificial intelligence, RISC-V silicon accelerators, and local machine intelligence. We provide bare-metal benchmarks and architectural teardowns for engineers deploying AI without cloud latency or subscription lock-in.

Our Mission: Deterministic Edge Silicon Over Cloud Subscriptions

As modern software systems increasingly push workloads toward centralized cloud APIs, engineers face spiraling egress fees, latency bottlenecks, and vendor dependencies. Edge Silicon Lab is dedicated to sovereign, local edge computation. Every teardown and benchmark published on this platform is grounded in:

  • Deterministic Benchmark Metrics: Measuring real-world TOPS/Watt, quantized model latency (INT8, FP16, INT4), tokens-per-second, and thermal throttling under sustained inference loads.
  • Silicon Architecture Teardowns: Evaluating dedicated NPU IP cores across Hailo-8, Google Coral TPU, NVIDIA Jetson Orin, Apple Neural Engine, and modern x86/ARM NPUs (Intel NPU, AMD XDNA, Qualcomm Oryon).
  • Local-First Toolchains: Auditing deployment pipelines including ONNX Runtime, TensorRT-LLM, OpenVINO, llama.cpp, and RKNN across edge SBCs, PCIe accelerator cards, and low-power microcontrollers.
  • Zero Vendor Sponsorship Bias: Benchmarking silicon objectively with open source code, reproducible test harnesses, and independent power consumption logging.

Editorial Leadership & Systems Architecture Board

Kieran Mercer — Principal Silicon Architect & Edge Computing Director

Kieran Mercer leads hardware teardowns, inference efficiency audits, and compiler toolchain benchmarks at Edge Silicon Lab. Bringing over a decade of hands-on embedded systems and microarchitecture experience spanning RISC-V compute, neural accelerators, and real-time computer vision pipelines, Kieran specializes in extracting maximum inference density per watt from localized silicon.

Absolute Editorial & Technical Independence

Edge Silicon Lab operates with complete editorial autonomy. We do not accept paid silicon reviews, sponsored benchmark tampering, or pre-arranged hardware verdicts. If a processor fails its advertised throughput under sustained thermal loads, our benchmark matrices document the exact failure points transparently.

For technical inquiries, silicon sample submissions, or benchmark harness requests, contact our engineering team at editorial@edgesiliconlab.com.