If you have spent any time scaling transformer models, multi-camera vision networks, or high-throughput real-time spatial analytics, you have almost certainly slammed headfirst into the silicon power wall. You tune your batch sizes, double-buffer your inputs, and throw six-figure GPUs at the cluster, only to watch your system hit thermal throttling limits long before the compute cores ever reach full utilization. It is a frustrating, expensive ceiling that leaves infrastructure teams burning cash on kilowatt-hours just to idle powerful silicon execution engines.

The root cause of this wall is not inadequate arithmetic logic; it is a fundamental law of microelectronics physics that legacy processor architectures refuse to address. For decades, compute vendors solved AI performance bottlenecks by shrinking transistors and cramming more Matrix Multiply-Accumulate (MAC) units onto monolithic dies. But in modern workloads, arithmetic is practically free. The true energy tax—the silent budget killer eating away 90% of your system’s power—is the physical movement of data across silicon wires between separate memory banks and compute units.

Why Is Data Movement Sucking 90% of the Energy Out of Your AI Hardware?

To understand why traditional hardware designs fail under modern spatial AI workloads, we have to look at the physical energy cost of moving a single bit across silicon. In a standard 5nm or 4nm semiconductor manufacturing process, executing a 32-bit or 8-bit floating-point (FP8) multiplication unit takes roughly 0.1 to 0.5 picojoules (pJ) of energy. Arithmetic is remarkably cheap because chip designers have optimized the physical layout of logic gates down to sub-nanometer geometries.

However, when that same bit of data has to travel across a physical wire—from an off-chip High Bandwidth Memory (HBM3) stack, across a interposer, through a bus controller, and into a GPU register file—the energy cost skyrockets to between 20 and 100 picojoules. Even inside a monolithic die, shuffling data across millimeters of copper interconnect to reach a centralized compute bank consumes orders of magnitude more power than the math itself.

This is the classic von Neumann bottleneck taken to an extreme scale. Traditional graphics processing units (GPUs) and conventional tensor accelerators treat memory and compute as two separate continents connected by massive, power-hungry superhighways. They spend billions of transistors building giant register files, complex cache hierarchies (L1/L2/L3), and ultra-wide memory buses just to keep the arithmetic units fed with data.

When you process continuous video streams, high-resolution spatial maps, or auto-regressive transformer tokens, your hardware is not bound by compute capacity; it is constantly stalled waiting for data to travel across those copper bridges. You end up paying for a 450-Watt thermal design power (TDP) budget where 400 Watts are squandered purely on charging and discharging micro-capacitances along silicon traces. Untether AI built the Boqueria architecture specifically to dismantle this paradigm by collapsing the physical distance between storage and arithmetic down to micrometers.

How Does Untether AI’s Boqueria Architecture Re-Engineer Spatial Math?

Untether AI’s Boqueria accelerator discards the von Neumann paradigm in favor of true “At-Memory Computing.” Instead of placing a massive block of compute logic on one side of the chip and a massive block of memory on the other, Boqueria intermixes memory and compute uniformly across a two-dimensional spatial array.

At the center of this design is a dense, distributed 238MB SRAM array. Embedded directly into the physical layout of this SRAM—within micrometers of the memory bitcells—are 1,458 custom, lightweight 64-bit RISC-V processor cores. Each processor core is tightly coupled to its own local memory block, transforming the chip into a massively parallel grid of self-contained compute elements.

Because the logic sits adjacent to the storage, the physical wires carrying weight matrices and activation tensors are extraordinarily short. Shorter wires mean drastically reduced parasitic capacitance, lower operational voltage requirements, and near-zero energy loss during bit transfers. This architectural shift unlocks three major physical advantages:

• 30 PetaBytes/Second Internal Bandwidth: By tapping into thousands of local memory banks simultaneously across the 2D grid, Boqueria achieves an aggregate memory bandwidth of 30 PB/s. This is hundreds of times greater than the internal bandwidth of state-of-the-art enterprise GPUs, ensuring that core execution units are never starved for data.
• 2 PetaFLOPS of FP8 Compute: Boqueria delivers up to 2 PFLOPS of FP8 precision (and up to 4 PFLOPS of INT4 compute), allowing complex vision models and large language model inference tasks to execute with high mathematical fidelity without exceeding tight edge or rack power envelopes.
• Sub-Micrometer Data Paths: Moving an activation value from SRAM to the execution unit requires traversing micrometers rather than millimeters or centimeters. This spatial proximity eliminates up to 90% of the data transport energy tax inherent in conventional AI accelerators.

Furthermore, each of the 1,458 RISC-V cores is augmented with custom spatial vector and matrix extension instructions. Rather than acting as general-purpose CPU cores that execute bloated instruction sets, these RISC-V micro-architectures are streamlined specifically for tensor operations, nonlinear activation functions, dynamic quantization scaling, and spatial data movement. The result is a chip that operates like a programmable physical medium where data flows spatially through a network of specialized processing nodes.

How Does Boqueria Stack Up Against Monolithic GPUs and Accelerators?

To evaluate how Boqueria fits into modern infrastructure, we must contrast its spatial at-memory microarchitecture against mainstream monolithic enterprise GPUs (such as the Nvidia L40S) and typical domain-specific systolic array accelerators.

When analyzing this contrast matrix, pay close attention to the structural handling of data flow. Traditional GPUs achieve high FLOPS ratings on paper, but keeping those execution units full requires enormous power budgets dedicated strictly to register file access and global memory buses. If your workload involves small batch sizes or continuous streaming inputs (e.g., 4K edge video inference or real-time robotics perception), the GPU’s deep cache hierarchy breaks down, exposing massive memory latency and wasting thermal overhead.

Systolic arrays attempt to solve this by pushing data sequentially from one processing element to the next. While efficient for fixed, rigid matrix multiplications, they struggle when handling dynamic spatial models, dynamic sparsity, or custom activation logic. Untether AI’s design balances flexible programmability with spatial efficiency: each of the 1,458 RISC-V nodes can independently execute spatial control logic, manipulate local vector registers, and route tensor fragments across the 2D grid with sub-nanosecond latency.

How Do You Compile and Deploy Production Models to Boqueria Silicon?

Hardware innovations are useless if your machine learning engineering team has to spend six months rewriting model architectures in custom assembly language. Untether AI addresses this challenge using an automated spatial compiler toolchain (imATRONIC) that transforms high-level compute graphs (PyTorch, ONNX, TensorFlow) directly into spatially mapped RISC-V execution pipelines.

Here is the concrete four-step workflow for compiling, partitioning, and deploying production models onto Boqueria silicon today.

Step 1: Graph Ingestion & Model Quantization

Start by exporting your trained PyTorch or Transformer model to a standard target graph (ONNX or TorchScript). The compiler ingests the computation graph and performs automatic FP8 or INT8 calibration using representative sample data.

Because Boqueria natively supports FP8 formats (both E4M3 and E5M2 variants), you can preserve non-linear activation dynamic ranges without falling back to power-hungry FP32 or FP16 logic. Run the quantization compiler via the SDK CLI:

untether-compiler ingest --model vision_transformer.onnx --target fp8_e4m3 --output quantized_graph.imx

Step 2: Spatial Graph Partitioning Across the 2D Core Grid

Once quantized, the spatial compiler maps the mathematical operations of your network across the physical topology of the chip. Instead of compiling a single monolithic execution binary, the SDK breaks the neural network layers into spatial tiles and assigns each tile to a cluster of the 1,458 RISC-V nodes.

During this stage, weight tensors are statically pre-loaded into the specific local SRAM cells immediately adjacent to the execution cores that will compute them. Weight transfers across PCIe during runtime are eliminated entirely. Activations are routed continuously through physical neighbor-to-neighbor connections across the chip grid.

Step 3: RISC-V Pipeline Kernel Generation

The compiler generates microcode for each individual RISC-V processing element. Custom vector operations (such as Spatial Convolution, Softmax, LayerNorm, and MatMul) are linked against optimized hardware primitives. You can verify memory distribution and core assignment density using the built-in spatial profiling utility:

untether-profile analyze --graph quantized_graph.imx --visualize-spatial-map

Review the output heatmap to ensure that memory usage is balanced across the 238MB SRAM grid and that no single spatial tile creates a latency hotspot or data routing bottleneck.

Step 4: Host Runtime Execution and Stream Pipeline Tuning

Finally, initialize the Untether AI C++ or Python runtime within your production inference service. The host processor (x86 or ARM server) is responsible only for feeding input activation streams (such as video frames or token IDs) into the PCIe endpoint memory region and reading back the inference predictions.

import untether_runtime as utr

Initialize Boqueria accelerator device context
device = utr.Device(device_id=0)
engine = device.load_engine("quantized_graph.imx")

Allocate pinned DMA buffers for continuous streaming
input_buffer = engine.create_input_buffer()
output_buffer = engine.create_output_buffer()

Push raw frame stream to spatial SRAM grid
input_buffer.write(preprocessed_tensor_data)
engine.execute_async(input_buffer, output_buffer)

Synchronize and extract inference results
engine.wait_completion()
predictions = output_buffer.read()

By delegating execution to the 1,458 spatial cores, host CPU utilization remains near zero, and latency stays strictly deterministic regardless of system load on the main host platform.

Frequently Asked Questions

What is At-Memory Computing, and how does it differ from In-Memory Computing?

At-Memory Computing places dedicated micro-processors and arithmetic execution logic directly adjacent (within micrometers) to standard, highly reliable SRAM bitcells on the same silicon die. In-Memory Computing attempts to perform analog arithmetic directly inside the memory array itself (using cell resistance or voltage drop). At-Memory preserves digital precision, full software programmability, and standard foundry CMOS processes while eliminating 90% of data movement energy.

What precision formats does the Untether AI Boqueria architecture natively support?

Boqueria provides native hardware support for FP8 (including both E4M3 and E5M2 standard formats), INT8, and INT4 numeric precisions. It can deliver up to 2 PFLOPS of FP8 performance or up to 4 PFLOPS of INT4 execution, allowing developers to balance inference throughput against precision requirements based on model sensitivity.

Why does Boqueria use 1,458 RISC-V cores instead of custom proprietary ALUs?

Using custom 64-bit RISC-V microprocessors provides a balance between spatial efficiency and flexible software programmability. Proprietary non-standard execution units often struggle with non-linear layers, custom activation functions, or evolving AI topologies. RISC-V offers an open, highly extensible instruction set architecture (ISA) that Untether AI augmented with specialized vector and tensor extensions without sacrificing compiler compatibility.

How does Boqueria achieve 30 PetaBytes/second of internal bandwidth?

Traditional chips rely on a unified memory bus connected to centralized memory banks. Boqueria distributes 238MB of SRAM across 1,458 independent, localized memory regions. Because all 1,458 local SRAM banks can be read from and written to concurrently by their adjacent RISC-V processors across a physical 2D grid, the aggregate on-chip memory throughput scales to an extraordinary 30 PetaBytes per second.