How does the Tenstorrent Wormhole RISC-V architecture challenge NVIDIA’s AI dominance?

The artificial intelligence semiconductor landscape has long suffered from proprietary software capture. NVIDIA’s CUDA ecosystem has acted as a formidable walled garden, locking enterprises, researchers, and cloud providers into specialized, expensive GPU architectures. However, visionary silicon architect Jim Keller (legendary designer of AMD Zen, Apple A4/A5, and Tesla Autopilot hardware) is challenging this paradigm at Tenstorrent.

Tenstorrent’s flagship processor, Wormhole, approaches AI acceleration not as an overgrown graphics card, but as a modular network of programmable mathematical nodes built upon open-source RISC-V instruction set architecture (ISA). By integrating native 100-Gigabit Ethernet optical routing directly onto the silicon die, Tenstorrent enables cards to interconnect into multi-teraflop computing fabrics without external switches. Cross-linking into our silicon benchmarks in Kneron KL720 NPU Sub-3W Transformer Inference Guide and referencing our processor audits in Snapdragon X Elite Hexagon NPU Architecture Audit, this guide explores the inner workings of Wormhole’s Tensix cores.

The Tensix Core: Five RISC-V Processors per Execution Block

The fundamental computational building block of Tenstorrent silicon is the Tensix Core. Rather than utilizing a single monolithic scheduler, each Tensix core is a decentralized, semi-autonomous computing engine containing:

• Five Programmable Baby RISC-V Cores: Three RISC-V cores are dedicated to data movement (Unpack, Pack, and Data Mover), while two cores manage computational control and instruction dispatch. This decouples arithmetic math from memory latency.
• Matrix Compute Engine (Matrix MO): A high-throughput tensor multiplication unit capable of executing 32×32 matrix operations in FP16, BFP8, BFP4, and INT8 formats.
• Vector Engine (Vector MO): A programmable SIMD vector processor handling activation functions (GELU, ReLU, Softmax) and element-wise tensor math.
• 1.5 MB Local SRAM Memory: Each core houses high-speed local SRAM. When combined across the 72-core grid, the chip provides over 108 MB of low-latency on-chip memory.

Network-on-Chip (NoC): Mesh Networking on Silicon

Traditional multi-core processors suffer from communication bottlenecks as core counts scale. If Core 1 wants to transmit an activation tensor to Core 64, data must travel across congested crossbar switches or centralized shared caches.

Wormhole implements a 2D Torus Network-on-Chip (NoC). Data packets move horizontally and vertically from core to adjacent core using packetized wormhole routing. More importantly, this 2D mesh does not stop at the silicon package boundary. The on-die 100GbE Ethernet controllers extend the on-chip NoC directly across physical cables. When two Wormhole PCIe cards are cabled together, their internal 2D mesh grids merge into a single seamless compute fabric. Software kernels address remote cores on adjacent cards using the identical memory-mapped I/O (MMIO) addresses as local on-die cores.

Baby RISC-V Micro-Architecture: Decoupled Data Movement

At the micro-architectural level, the secret to Tensix core efficiency is the complete separation of data orchestration from mathematical execution. In standard CPUs and GPUs, ALUs frequently stall waiting for cache misses or memory translation lookaside buffer (TLB) lookups. In a Tensix core, five microscopic, customized 32-bit RISC-V cores (referred to by Tenstorrent as “Baby RISC-V” processors) operate in parallel inside each core:

• Decoupled Memory Movement: Three of the Baby RISC-V cores are dedicated exclusively to driving the local Direct Memory Access (DMA) engines. They calculate tensor strides, pre-fetch matrix tiles from external GDDR6 memory or neighboring cores across the NoC, and unpack compressed tensor formats directly into local L1 SRAM.
• Unstalled Math Execution: The remaining two Baby RISC-V cores manage instruction issue to the SIMD vector unit and matrix multiplication engines. Because the DMA cores ensure that local L1 SRAM is perpetually pre-loaded with the exact operands needed for the next computational cycle, the math execution units operate with near 100% duty cycle efficiency, completely avoiding the stall cycles that degrade conventional GPU performance.
• Custom Vector Extensions: The Baby RISC-V cores implement proprietary instruction extensions tailored for deep learning math, enabling hardware-level execution of non-linear activations (GELU, SILU, Softmax) and dynamic tensor slicing without calling external firmware libraries.

Thermal Profiles, Power Envelopes, and Workstation Deployment

Deploying Tenstorrent Wormhole in production environments presents unique physical advantages over bulky datacenter accelerators. The Wormhole n150 card operates within a conservative 160W Total Board Power (TBP) envelope, while the dual-chip n300 card draws 300W under peak synthetic stress:

1. Standard PCIe Form Factor: Unlike NVIDIA H100/B200 SXM modules that require multi-thousand-dollar liquid cooling manifolds or 48V power shelves, Wormhole cards fit directly into standard dual-slot PCIe Gen4 x16 slots found in standard ATX workstation motherboards. Standard 8-pin PCIe or 12V-2×6 power connectors supply all required current.
2. Acoustic and Thermal Engineering: Workstation editions of the n150 feature active axial cooling fans that maintain operating temperatures below 75°C under sustained token generation workloads while operating at noise levels under 38 dBA. This allows machine learning researchers and software developers to keep high-performance RISC-V AI hardware directly at their desks rather than leasing noisy remote server rack space.

The Strategic Value of the Open-Source TT-Metalium Stack

Tenstorrent’s greatest competitive moat may ultimately be its software philosophy. Recognizing that developers resent CUDA’s proprietary monopoly, Tenstorrent open-sourced its entire stack under the Apache 2.0 license:

• TT-Metalium (Bare-Metal Programming): Provides direct C++ APIs allowing developers to write custom SIMD math kernels directly to the Tensix RISC-V cores, bypassing heavy runtime abstractions.
• TT-Buda (High-Level Framework Integration): Automatically ingests PyTorch, JAX, and ONNX models, performing graph partitioning and memory allocation across the Tensix mesh.
• Sovereign Silicon Independence: Because RISC-V is an open, international instruction set free from export embargoes or proprietary licensing fees, Tenstorrent architecture represents a sovereign alternative for international enterprises, universities, and open-source AI researchers seeking immunity from proprietary cloud and hardware gatekeepers.

Frequently Asked Questions

What is the difference between the Tenstorrent Wormhole n150 and n300 cards?

The n150 is a standard single-slot PCIe card containing one Wormhole processor with 12GB GDDR6 memory. The n300 is a dual-slot PCIe card containing two Wormhole processors interconnected on the same PCB, delivering 24GB GDDR6 memory and double the compute.

Can Tenstorrent Wormhole run Hugging Face transformer models out of the box?

Yes. The TT-Buda and TT-Metalium software stacks include native automated graph compilers for major transformer models including Llama 3, Mistral, BERT, Whisper, and Stable Diffusion.

Why did Jim Keller choose RISC-V over ARM for Tenstorrent?

RISC-V is a royalty-free, completely customizable open-standard instruction set. It allowed Tenstorrent to strip away legacy instructions and design ultra-minimalist, hyper-efficient custom micro-controllers (Baby RISC-V) optimized strictly for data movement and tensor math.